The present invention relates to a semiconductor memory device, and more particularly, to a decoder circuit in the memory device.
The storage capacity of semiconductor memory devices becomes greater and greater in recent developments, and efforts are being made to increase the integration density of the integrated circuit chip without increasing the chip area through the development of techniques of miniaturizing functional elements, wiring and so forth.
It is, however, apparent from practical experiences that an increase in the storage capacity inevitably causes an increase in chip area. Owing to the miniaturization and the increase in the chip area, the chip yield of the memory device has been remarkably reduced. A considerable number of defects in the semiconductor memory device which cause the chip yield reduction are attributable to the failure of memory cells of bits which account for not larger than 1% of the whole memory bits, such as the failure of one to several bits or the failure of one to several words.
As measures to salvage such a failure, there are known a redundancy arrangement that a chip is provided with a spare memory array for replacing any defective bits thereby, and a method (mostly good) that utilizes the greater part of operative bits while eliminating some defective bits. The conventional memory, however, cannot efficiently realize the above-mentioned saving methods. The reasons for this are attributable to various restrictions imposed for attaining a memory of great storage capacity.
First of all, one-transistor type cells are usually employed for such a large-capacity memory, and the area per bit is small in this case. However, the cells are of dynamic type, and hence, the written information disappears when a predetermined time has elapsed. Therefore, it is necessary to execute a rewriting cycle called "refreshing" within this time. In this refreshing cycle, by accessing one word line of a memory matrix, all the memory cells connected to the one word line are simultaneously refreshed. For example, a dynamic memory of 16K bits has a memory matrix constituted by 128 rows by 128 columns. In the refreshing cycle, the rows of the matrix are accessed one by one, and all the bits of the memory matrix are refreshed by 128 accesses in total. During this refreshing cycle, the other bits cannot be accessed. Therefore, the dynamic memory is required to hold down the number of refreshing cycles, i.e., the number of rows of the memory matrix to a value smaller than a predetermined value. For example, in a memory of 64K bits, a memory matrix of 128 rows by 512 columns is constituted to prevent any increase in number of refreshing cycles. In order to prevent the chip from taking long and narrow shape in the row direction owing to the above arrangement, such an arrangement is employed that the memory matrix is divided into two parallel arrays each having 128 rows by 256 columns, and each array is provided with row decoders so that the 512 (256.times.2) cells in the both arrays are simultaneously refreshed by selecting one row in each array.
Moreover, one-transistor type cells have been becoming smaller in size in proportion to the increase have been in the storage capacity, and hence there occured a restriction due to the fact that layout pitches of decoders are larger than that of cells. More specifically, since it is impossible to dispose one decoder and one word line in the same direction, one decoder is allotted to a plurality of word lines through a plurality of switches, respectively, and only one of these word lines is brought to the selection level by energizing one of these switches, thereby to solve the problem of the pitch difference.
For example, in an RAM of 16K bits, two word lines are connected to one decoder through two switches, respectively, and in an RAM of 64K bits four word lines are connected to one decoder through four switches, respectively. When a plurality of word lines are led out from one decoder, the conventional physical arrangement of word lines on a memory matrix is such that the word lines coming out of the same decoder are adjacent to each other. Such an arrangement offers a disadvantage in manufacturing a memory having the above-mentioned redundancy circuits or a memory adopting the most good method.
There is an unignorable amount of failure due to short circuits between the adjacent word lines in a defective mode in which some memory cells are defective. In such a defect mode, the conventional arrangement unfavorably causes a large number of word line failures. If it is considered that short circuits occur with an equal probability between all the adjacent word lines, in the above-mentioned RAM of 64K bits, for example, 3/4 of the short circuits occur between the adjacent word lines connected to the same decoder. In such a case, when either one of the adjacent word lines short-circuiting with each other in one array is in the selective state, the other word line short-circuiting with the one word line is simultaneously brought into the selective state. At this time, a current undesirably flows between two switches connected between these two word lines and the decoder, respectively, so that two control signal lines for selectively driving the two switches are simultaneously energized. Accordingly, at this time, also in the other array, two of four word lines connected to a selected decoder are erroneously selected at the same time. As a result, four word lines in total are brought into the selective state. Thus, the failure of one pair of word lines accompanies the failure of another pair of word lines disadvantageously. For this reason, it is impossible to electrically determine the two word lines short-circuiting with each other from the four word lines. Accordingly, these two pairs of word lines must be replaced with two pairs of redundancy circuits, and therefore, the conventional method is not efficient.